SIAM PP20 – The Many Faces of Simulation for HPC Minisymposium

Minisymposium: The Many Faces of Simulation for HPC

Saturday February 15, 2020

Organizers:
Rafael Ferreira da Silva
University of Southern California, U.S.
Frédéric Suter
CNRS, France


Abstract – In the field of HPC research and development, simulation has mainly been used for the purpose of evaluating and comparing the performance of application implementations and of the algorithms therein. While this use remains critical, for good reasons, many other compelling use cases have emerged. These have often been made possible by recent advances in the simulation methodologies at the core of available simulation frameworks. Examples of new areas in which simulation has become a compelling proposition include debugging and verification, application/simulation co-design, and HPC education. In this multi-part mini-symposium, we bring together researchers who have contributed to traditional and explored emerging uses of simulation of HPC systems and applications. The objective is for them to share their experiences, present recent results, identify areas of convergence, and discuss future directions.


Session 1

https://meetings.siam.org/sess/dsp_programsess.cfm?SESSIONCODE=67786

10:40-11:00 The Many Faces of Simulation for HPC
Frédéric Suter, CNRS, France;
Rafael Ferreira da Silva, University of Southern California, U.S.

11:05-11:25 Teaching Parallel and Distributed Computing Concepts in Simulation
Henri Casanova, University of Hawaii, U.S.

11:30-11:50 Fast and Faithful Performance Prediction of MPI Applications: the HPL Case Study
Tom Cornebize, Université Grenoble Alpes, France;
Arnaud Legrand, CNRS, France;
Franz Christian Heinrich, Inria, France

11:55-12:15 Power-Aware Scheduling with Slurm: Simulation and Practice
Tapasya Patki, Lawrence Livermore National Laboratory, U.S.


Session 2

https://meetings.siam.org/sess/dsp_programsess.cfm?SESSIONCODE=67787

1:50-2:10 Faithful Performance Prediction of a Dynamic Task-Based Runtime System, an Opportunity for Task Graph Scheduling
Samuel Thibault, LaBRI, France;
Luka Stanisic, Inria Bordeaux Sud-Ouest, France;
Arnaud Legrand, CNRS, France;
Brice Videau, INRIA Grenoble Rhône-Alpes, France;
Jean-François Méhaut, Universite Joseph Fourier, France

2:15-2:35 New Horizons for Debugging Long-running Parallel Programs: DMTCP and SimGrid
Gene Cooperman and Rohan Garg, Northeastern University, U.S.

2:40-3:00 Application-simulation co-design for performance and correctness evaluation
Luigi Genovese, CEA, France;
Augustin Degomme, CEA Grenoble

3:05-3:25 To Be Defined
TBD

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